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ISL95710
Digitally Controlled Potentiometer (XDCPTM)
Data Sheet August 31, 2006 FN8240.3
Terminal Voltage 2.7V to 5V, 128 Taps, Up/Down Interface
The Intersil ISL95710 is a digitally controlled potentiometer (XDCP). The device consists of a resistor array, wiper switches, a control section, and nonvolatile memory. The wiper position is controlled by a Up/Down interface. The potentiometer is implemented by a resistor array composed of 127 resistive elements and a wiper switching network. Between each element and at either end are tap points accessible to the wiper terminal. The position of the wiper element is controlled by the CS, U/D, and INC inputs. The position of the wiper can be stored in nonvolatile memory and then be recalled upon a subsequent power-up operation. The device can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including: * Industrial and automotive control * Parameter and bias adjustments * Amplifier bias and control
Features
* Non-Volatile Solid-State Potentiometer * Up/Down Interface with Chip Select Enable * DCP Terminal Voltage 2.7V to 5.5V * 128 Wiper Tap Points - Wiper position stored in nonvolatile memory and recalled on power-up * 127 Resistive Elements - Typical RTOTAL tempco = 50ppm/C - End to end resistance range 20% * Low Power CMOS - Standby current, 1A - Active current, 3mA max - VCC = 2.7V to 5.5V - V- = -2.7V to -5.5V * High Reliability - Endurance, 200,000 data changes per bit - Register data retention, 50 years * RTOTAL Values = 10k, 50k
Pinout
ISL95710 (10 LD MSOP) TOP VIEW
* Package - 10 Ld MSOP - Pb-free plus anneal (RoHS compliant)
INC VCC RL RW RH
U/D VGND CS NC
1 2 3 4 5
10 9 8 7 6
Ordering Information
PART NUMBER (Notes 1, 2) ISL95710WIU10Z ISL95710UIU10Z NOTES: 1. Add "-T" suffix for tape and reel. 2. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. PART MARKING AKR AKP RESISTANCE OPTION () 10k 50k TEMP. RANGE (C) -40 to +85 -40 to +85 PACKAGE (Pb-Free) 10 Ld MSOP 10 Ld MSOP PKG. DWG. # M10.118 M10.118
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil, Inc. Copyright Intersil Americas Inc. 2005, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL95710 Block Diagram
U/D V- (ANALOG VOLTAGE) VCC INC CS UP/DOWN (U/D) INCREMENT (INC) DEVICE SELECT (CS) CONTROL AND MEMORY RH 7-BIT NONVOLATILE MEMORY 7-BIT UP/DOWN COUNTER 127 126 125 124 ONE OF 128 DECODER 2 GND (GROUND) GENERAL STORE AND RECALL CONTROL CIRCUITRY 1 0 RL RW DETAILED TRANSFER GATES RESISTOR ARRAY RH
RW
RL
VGND
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 SYMBOL U/D VGND CS NC RH RW RL VCC INC DESCRIPTION Controls the direction of wiper movement and whether the counter is incremented or decremented Negative bias voltage for the potentiometer wiper control Ground Chip select. The device is selected when the CS input is LOW. Also used to initiate a nonvolatile store No Connect. Pin is to be left unconnected A fixed terminal for one end of the potentiometer resistor The wiper terminal which is equivalent to the movable terminal of a potentiometer A fixed terminal for one end of the potentiometer resistor Positive logic supply voltage Increment input; negative edge triggered
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ISL95710
Absolute Maximum Ratings
Temperature under bias . . . . . . . . . . . . . . . . . . . . . .-65C to +135C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Voltage on CS, INC, U/D and VCC with respect to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +6V Voltage on V- (referenced to GND) . . . . . . . . . . . . . . . . . . . . . . . -6V V = |V(RH)-V(RL)| . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V Lead temperature (soldering 10 seconds) . . . . . . . . . . . . . . . . 300C IW (10 seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6mA ESD (Mil-Std 883, Method 3015) . . . . . . . . . . . . . . . . . . . . . . . .>2kV ESD Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>150V
Thermal Information
Thermal Resistance (Typical, Note 3) MSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . JA (C/W) +170
Recommended Operating Conditions
Temperature Range (Industrial) . . . . . . . . . . . . . . . . .-40C to +85C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7V to -5.5V
CAUTION: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device (at these or any other conditions above those listed in the operational sections of this specification) is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
NOTE: 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Analog Specifications
SYMBOL RTOTAL
Over recommended operating conditions unless otherwise stated. TEST CONDITIONS W option U option MIN TYP (Note 1) 10 50 -20 IDCP = 1mA T = -40C to +85C VV- = -5.5V; VCC = +5.5V, wiper current = (VCC-V-)/RTOTAL 70 10/10/25 Voltage at pins; V- to VCC -1 0.1 1 50 VCC 200 +20 MAX UNIT k k % ppm/C V pF A
PARAMETER RH to RL resistance
RH to RL resistance tolerance TCR Resistance Temperature Coefficient (Note 12, 13) VRH,VRL RW CH/CL/CW (Note 13) ILkgDCP RH,RL terminal voltage Wiper resistance Potentiometer Capacitance Leakage on DCP pins
VOLTAGE DIVIDER MODE (V- @ RL; VCC @ RH; Voltage at RW = VRW unloaded) INL (Note 6) DNL (Note 5) ZSerror (Note 3) FSerror (Note 4) Integral non-linearity Differential non-linearity Zero-scale error W, U options W option U option Full-scale error W option U option DCP Register set at 63d, T = -40C to +85C -1 -0.5 0 0 -4 -2 1 0.5 -1 -0.5 4 1 0.5 4 2 0 0 LSB (Note 2) LSB (Note 2) LSB (Note 2) LSB (Note 2) ppm/C
TCV Ratiometric Temperature Coefficient (Notes 7, 13)
RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) RINL (Note 11) RDNL (Note 10) Roffset (Note 9) Integral non-linearity Differential non-linearity Offset DCP register set between 20 hex and 5F hex. Monotonic over all tap positions W, U options DCP Register set to 00 hex, W option DCP Register set to 00 hex, U option -1 -0.5 0 0 2 0.5 1 0.5 5 2 MI (Note 8) MI (Note 8) MI (Note 8)
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ISL95710
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL ICC1 IV-1 ICC2 IV-2 ICCSB PARAMETER TEST CONDITIONS MIN TYP (Note 1) MAX 500 -100 500 -3 1 1 -5 -2 -10 -300 -2.5 2.5 -0.2 10 UNIT A A A mA A A A A A A V V V/ms
VCC supply current, volatile write/read CS = VIL, U/D = VIL or VIH and INC = VIL or VIH, RL, RH, RW not connected V- supply current, volatile write/read VCC supply current, nonvolatile write V- supply current, nonvolatile write VCC current (standby) CS = VIL, U/D = VIL or VIH and INC = VIL or VIH, RL, RH, RW not connected U/D = VIL or VIH and INC = VIH, CS = transitions from VIL to VIH. RL, RH, RW not connected U/D = VIL or VIH and INC = VIH, CS = transitions from VIL to VIH. RL, RH, RW not connected VCC = +5.5V, I2C Interface in Standby State VCC = +3.6V, I2C Interface in Standby State
IV-SB
V- current (standby)
V- = -5.5V, CS = VIH V- = -3.6V, CS = VIH
ILkgDig IIL_CS Vpor
Leakage current, at pins INC, CS, and VIL or VIH applied at pin U/D Leakage at CS, input low Power-on recall for both V- and VCC VIL = 0V VVCC
V- Ramp
V- ramp rate
EEPROM SPECS EEPROM Endurance EEPROM Retention 3-WIRE INTERFACE SPECS VIL VIH Hysteresis (Note 13) Cpin INC, CS, and U/D input buffer LOW voltage INC, CS, and U/D input buffer HIGH voltage INC, CS, and U/D input buffer hysteresis INC, CS, and U/D pin capacitance -0.3 0.7*VCC 0.15* VCC 10 0.3*VCC VCC+ 0.3 V V V pF Temperature +75C 200,000 50 Cycles Years
AC Electrical Specifications
SYMBOL tCl tlD tDI tlL tlH tlC tCPHS (Note 14) tCPHNS CS to INC setup
VCC = 5V 10%, TA = Full Operating Temperature Range unless otherwise stated PARAMETER MIN 100 100 1 1 1 1 20 1 TYP (Note 1) MAX UNIT ns ns s s s s ms s
INC HIGH to U/D change U/D to INC setup INC LOW period INC HIGH period INC inactive to CS inactive CS deselect time (STORE) CS deselect time (NO STORE)
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ISL95710
AC Electrical Specifications
SYMBOL tIW tCYC tR, tF NOTES: 1. Typical values are for TA = +25C and 3.3V supply voltage. 2. LSB: [V(RW)127 - V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 3. ZS error = (V(RW)0- V-)/LSB. 4. FS error = [V(RW)127 - V+]/LSB. 5. DNL = [V(RW)i - V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 6. INL = V(RW)i - (i * LSB - V(RW)0)/LSB for i = 1 to 127. Max ( V ( RW ) i ) - Min ( V ( RW ) i ) 10 6 7. TC V = ----------------------------------------------------------------------------------------------x ---------------[ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] 2 125C for i = 16 to 120 decimal. Max ( ) is the maximum value of the wiper voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 8. MI = |R127 - R0| /127. R127 and R0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively. 9. Roffset = R0/MI, when measuring between RW and RL. Roffset = R127/MI, when measuring between RW and RH. 10. RDNL = (Ri - Ri-1)/MI -1, for i = 16 to 127. 11. RINL = [Ri - (MI * i) - R0]/MI, for i = 16 to 127. 6 [ Max ( Ri ) - Min ( Ri ) ] 10 12. TC = --------------------------------------------------------------- x ---------------R [ Max ( Ri ) + Min ( Ri ) ] 2 125C for i = 16 to 127, T = -40C to +85C. Max ( ) is the maximum value of the resistance and Min ( ) is the minimum value of the resistance over the temperature range. 13. This parameter is not 100% tested. 14. tCPHS is the minimum cycle time to be allowed for any non-volatile Write by the user. It is the time from a valid STORE condition to the end of the self-timed internal non-volatile write cycle. No CS or INC changes should be allowed. INC to RW change INC cycle time INC input rise and fall time 2 500 VCC = 5V 10%, TA = Full Operating Temperature Range unless otherwise stated (Continued) PARAMETER MIN TYP (Note 1) 100 MAX 500 UNIT s s s
Symbol Table
WAVEFORM INPUTS Must be steady OUTPUTS Will be steady
May change from Low to High May change from High to Low
Will change from Low to High Will change from High to Low
Don't Care: Changes Allowed
Changing: State Not Known
N/A
Center Line is High Impedance
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FN8240.3 August 31, 2006
ISL95710 A.C. Timing
CS tCYC tCI INC tID tDI tF tIL tIH tIC tCPHS 90% 90% 10% tR
tCPHNS
U/D tIW RW MI (1)
NOTE (1): MI IN THE TIMING DIAGRAM REFERS TO THE MINIMUM INCREMENTAL CHANGE IN THE WIPER POSITION.
Typical Performance Curves
120 Irw=0.6mA 100
WIPER RESISTANCE ()
T=85C
0.6 T = 85C
80 60
Isb (A)
0.5 T = 25C T = -40C 0.4
40 20 0 0 20 40 60 80
T=25C T=-40C
100
120
0.3 2.7
3.2
3.7
4.2
Vcc, V
4.7
5.2
TAP POSITION (DECIMAL)
FIGURE 1. WIPER RESISTANCE vs TAP POSITION [I(RW) = VCC/RTOTAL] for 10k (W)
FIGURE 2. STANDBY ICC vs VCC
0.2 Vrh=5.5V, Vrl=-5.5V 0.1
DNL (LSB) INL (LSB)
0.2 Vrh=5.5V, Vrl=-5.5V 0.1
0
0
-0.1 Vrh=2.7V, Vrl=-2.7V -0.2 0 20 40 60 80 100 120
TAP POSITION (DECIMAL)
-0.1 Vrh=2.7V, Vrl=-2.7V -0.2 0 20 40 60 80 100 120
TAP POSITION (DECIMAL)
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10k (W)
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ISL95710 Typical Performance Curves
1.6 Vrh=2.7V, Vrl=-2.7V, 10k 1.2
ZSerror (LSB) FSerror (LSB) (Continued)
0 -0.4 Vrh=5.5V, Vrl=-5.5V, 10k -0.8 -1.2 -1.6 Vrh=2.7V, Vrl=-2.7V, 10k -2 -40
0.8 Vrh=5.5V, Vrl=-5.5V, 10k 0.4
0 -40
-20
0
20
40
60
80
-20
0
20
40
60
80
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 5. ZSerror vs TEMPERATURE
FIGURE 6. FSerror vs TEMPERATURE
0.1 T=25C 0.05
RDNL (LSB)
1 Vcc=2.7V, V-=-2.7V 0.8 0.6
RINL (LSB)
T=25 C Vcc=2.7V, V-=2 7V
0
0.4 0.2 0 -0.2 Vcc=5.5V, V-=5 5V 0 50
TAP POSITION (DECIM AL)
-0.05 Vcc=5.5V, V-=-5.5V -0.1 0 20 40 60 80 100 120
TAP POSITION (DECIMAL)
100
FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W)
FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 10k (W)
END TO END RTOTAL CHANGE (%)
1 Idcp= 0.57mA 0.5
TCv (ppm/C)
100 80 60 40 10k 20 50k 0 -20 0 20 40 60 80 16 36 56 76 96 116
TEMPERATURE (C) TAP POSITION (DECIMAL)
0 Idcp= 1.16mA -0.5
-1 -40
FIGURE 9. END TO END RTOTAL % CHANGE vs TEMPERATURE
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
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FN8240.3 August 31, 2006
ISL95710 Typical Performance Curves
200 10k 150
TCr (ppm/C) (Continued)
100
50 50k 0 16 36 56 76 96
FIGURE 12. FREQUENCY RESPONSE (1.8MHz)
TAP POSITION (DECIMAL)
FIGURE 11. TC FOR RHEOSTAT MODE IN ppm
FIGURE 13. WIPER MOVEMENT
FIGURE 14. LARGE SIGNAL SETTLING TIME
Power Up and Down Requirements
In order to prevent unwanted tap position changes, or an inadvertent store, bring the CS and INC high before or concurrently with the VCC pin on power-up. The potentiometer voltages must be applied after this sequence is completed. During power-up, the data sheet parameters for the DCP do not fully apply until 1ms after VCC reaches its final value. The VCC ramp spec is always in effect.
RW
Rw is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the wiper counter.
Up/Down (U/D)
The U/D input controls the direction of the wiper movement and whether the wiper counter is incriminated or decremented.
Pin Descriptions
RH and RL
The high (RH) and low (RL) terminals of the ISL95710 are equivalent to the fixed terminals of a mechanical potentiometer. The terminology of RL and RH references the relative position of the terminal in relation to wiper movement direction selected by the U/D input and not the voltage potential on the terminal.
Increment (INC)
The INC input is negative-edge triggered. Toggling INC will move the wiper and either increment or decrement the wiper counter in the direction indicated by the logic level on the U/D input.
Chip Select (CS)
The device is selected when the CS input is LOW. The current wiper counter value is stored in nonvolatile memory when CS is returned HIGH while the INC input is also HIGH. After the store operation is complete the ISL95710 will be
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FN8240.3 August 31, 2006
ISL95710
placed in the low power standby mode until the device is selected once again. adjustments might be based on user preference, system parameter changes due to temperature drift, etc. The state of U/D may be changed while CS remains LOW. This allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. During initial power-up CS must go high along with or before VCC to avoid an accidental store generation.
TABLE 1. MODE SELECTION CS L L H H X L H H L L INC U/D H L X X X X H L Wiper up Wiper down Store wiper position Standby current No store, return to standby Standby Wiper up one position (not recommended) Wiper down one position (not recommended) MODE
Principles of Operation
There are three sections of the ISL95710: the input control, wiper counter and decode section; the nonvolatile memory; and the resistor array. The input control section operates as an up/down counter. The output of this wiper counter is decoded to turn on a electronic switch connecting a point on the resistor array to the wiper output. The contents of the wiper counter can be stored in nonvolatile memory and retained for future use. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The wiper, when at either fixed terminal, acts like its mechanical equivalent and does not move beyond the last position. The wiper counter does not wrap around when clocked to either extreme. The electronic switches on the device operate in a "make before break" mode when the wiper changes tap positions. If the wiper is moved several positions, multiple taps are connected to the wiper for tIW (INC to RW change). The RTOTAL value for the device can temporarily be reduced by a significant amount if the wiper is moved several positions. When the device is powered-down, the last wiper position stored will be maintained in the nonvolatile memory. When power is restored, the contents of the memory are recalled and the wiper is set to the value last stored.
Instructions and Programming
The INC, U/D and CS inputs control the movement of the wiper along the resistor array. With CS set LOW the device is selected and enabled to respond to the U/D and INC inputs. HIGH to LOW transitions on INC will increment or decrement (depending on the state of the U/D input) a seven bit wiper counter. The output of this wiper counter is decoded to select one of 128 wiper positions along the resistive array. The value of the wiper counter is stored in nonvolatile memory whenever CS transitions HIGH while the INC input is also HIGH. The system may select the ISL95710, move the wiper and deselect the device without having to store the latest wiper position in nonvolatile memory. After the wiper movement is performed as described above and once the new position is reached, the system must keep INC LOW while taking CS HIGH. The new wiper position will be maintained until changed by the system or until a power-up/down cycle recalls the previously stored data. This procedure allows the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. The
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FN8240.3 August 31, 2006
ISL95710 Mini Small Outline Plastic Packages (MSOP)
N
M10.118 (JEDEC MO-187BA)
10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
E1 -BE
INCHES SYMBOL MIN 0.037 0.002 0.030 0.007 0.004 0.116 0.116 0.187 0.016 10 0.003 0.003 5o 0o 15o 6o MAX 0.043 0.006 0.037 0.011 0.008 0.120 0.120 0.199 0.028 A
ABC
MILLIMETERS MIN 0.94 0.05 0.75 0.18 0.09 2.95 2.95 4.75 0.40 10 0.07 0.07 5o 0o 15o 6o MAX 1.10 0.15 0.95 0.27 0.20 3.05 3.05 5.05 0.70 NOTES 9 3 4 6 7 Rev. 0 12/02
INDEX AREA
12 TOP VIEW
0.20 (0.008)
A1 A2
4X
0.25 (0.010) GAUGE PLANE SEATING PLANE -C-
R1 R
b c D E1
A
A2
4X
L L1
e E L L1 N R
0.020 BSC
0.50 BSC
A1
-He D
b
0.10 (0.004) -A0.20 (0.008)
C
SEATING PLANE
0.037 REF
0.95 REF
C a C L E1
C
R1
SIDE VIEW
-B-
0.20 (0.008)
CD
END VIEW
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension "D" does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B to be determined at Datum plane
11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 10
FN8240.3 August 31, 2006

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